PLL Clock Generator ICs with Built-In Divider/Multiplier Circuits (Low Oscillation)
The XC25BS5 series are high frequency, low power consumption PLL clock generator ICs with divider circuits & multiplier PLL circuits.
Laser trimming gives the option of being able to select from divider ratios (M) of 1,3 to 2047 and multiplier ratios (N) of 6 to 2047.
Output frequency (Q0) is equal to reference oscillation (fCLKin) multiplied by N/M, within a range of 3MHz to 30MHz. Q1 output is selectable from input reference frequency (f0), input reference frequency/2 (f0/2), GND (GND), and comparative frequencies (f0/M). Further, comparative frequencies, within a range of 12KHz to 500KHz, can be obtained by dividing the reference oscillation. By halting operation via the CE pin, consumption current can be controlled and output will be one of high-impedance.
|Divider Ratio(M)||Selectable from divisions of 1,3~2047|
|Multiplier Ratios(N)||Selectable from multiplications of,6~2047|
|Output||3 state,Q1 output selectable from input reference oscillation, input reference oscillation/2, GND, comparative frequencies|
|Operating Voltage Range||2.97V～5.5V|
|Low Quiescent Current||CMOS (standby function included)|
|Package||SOT-26||Number of Pins||6|
|Pcs/Reel||3,000||Package Size(mm)||2.8 x 2.9 x 1.3|
|Package||USP-6B||Number of Pins||6|
|Pcs/Reel||3,000||Package Size(mm)||1.8 x 2.0 x 0.6|